Zynq i2c tutorial. The way I did it was get the sources for the i2c-tools package on Ubuntu/Debian. $ sudo apt-get source i2c-tools Inside the directory, there will be a include directory and a tools directory. The include directory has the defines for i2c and smbus. In the tools directory is the source, you need to compile that with the cross compiler.

Zybo Z7-20. ZYNQ-7020を搭載した開発用ボード。. CPUはCortex-A9 x 2個. Vivado Design Suite. 複数のツールから構成される、Xilinxの設計開発環境。. 主に使うのは、以下の2つ. Vivado: RTLを書いたり、配置配線をする。. これでハードウェアを作る. Xilinx SDK: Vivadoが吐き出した ...

Zynq i2c tutorial. This offering can be used in two ways: The Zynq SoC PS can be used in a standalone mode, without attaching any additional fabric IP. IP cores can be instantiated in fabric and attached to the Zynq PS as a PS+PL combination. This chapter looks at how to develop an embedded system with only the processing system (PS) of the Zynq®-7000 SoC.

Add the Zynq IP & GPIO Blocks. 3.1) Click the Add IP button and search for ZYNQ. Double click on ZYNQ7 Processing System to place the bare Zynq block. 3.2) Click the Run Block Automation link and click OK. This will use the board files and correctly configure the ZYNQ processor for the Arty-Z7.

Introduction. This page provides information about the Cadence I2C driver which can be found on Xilinx Git and mainline as i2c-cadence.c. Zynq has two I2C hard IP. I2C can be used as a master with this linux driver. There is support for repeated start with some limitations.Starting the Board. Verify hardware setup—see User Guides for each board above. Board should be powered off at the start of these instructions. Set mode switch SW6 to 0010 (QSPI32). See available boot modes below. Connect to power and the board’s 6-pin power supply (J52) and power on board.

U-Boot 2018.01 Xilinx ZynqMP ZCU102 rev1.0 I2C: ready DRAM: 4 GiB EL Level: EL2 Chip ID: zuunknow ** Bad device mmc 0 ** Using default environment In: serial@ff000000 Out: serial@ff000000 Err: serial@ff000000 Model: ZynqMP ZCU102 Rev1.0 Board: Xilinx ZynqMP Bootmode: JTAG_MODE Net: ZYNQ GEM: ff0e0000, phyaddr c, interface rgmii-id eth0: ethernet@ff0e0000 U-BOOT for xilinx-zcu102-2018_1 BOOTP ...The controller is set as Master transmitter. Enable the PS IIC in the Zynq-7000/Zynq UltraScale+ device. Make sure that SCL is configured for either 100 kHz or 400 kHz frequency. Set the control register for the Master transmitter controller. Check if the interrupts are clear and that the clock dividers are configured for the actual SCL.Navigate to the Libraries icon on the left bar of the Arduino IDE. Search "LiquidCrystal I2C", then find the LiquidCrystal_I2C library by Frank de Brabander. Click Install button to install LiquidCrystal_I2C library. Copy the above code and open with Arduino IDE. Click Upload button on Arduino IDE to upload code to Arduino. See the result on LCD.Processing System. All Zynq devices have the same basic architecture, and all of them contain, as the basis of the processing system, a dual-core ARM Cortex-A9 processor. This is a 'hard' processor — it exists as a dedicated and optimised silicon element on the device. For comparison purposes, the alternative to a hard processor is a ...May 8, 2023 · This library provides GPIO, I2C, SPI, PWM/Timer and UART functionality. All of these libraries follow the same design. Each defines a type which represents a handle to the device. *_open functions are used in situations where there is an I/O switch in the design and takes a set of pins to connect the device to. The number of pins depends on …Nov 18, 2021 · What is FSBL? First St age Bootloader (FSBL) for Zynq UltraScale+ MPSoC configures th e FPGA with hardware bitstream (if it exists) and loads the Operating System (OS) Image or Standalone (SA) Image or 2nd Stage Boot Loader image from the non-volatile memory (NAND/SD/eMMC/QSPI) to Memory (DDR/TCM/OCM) and takes …Sep 23, 2021 Knowledge. Title. 51779 - Zynq-7000 SoC - Example Designs and Tech Tips. Description. This answer record keeps track of all current Example Designs and Tech Tips available for Zynq-7000 SoC. An Example Design is an answer record that provides technical tips to test a specific functionality on Zynq-7000 devices.What is FSBL? First St age Bootloader (FSBL) for Zynq UltraScale+ MPSoC configures th e FPGA with hardware bitstream (if it exists) and loads the Operating System (OS) Image or Standalone (SA) Image or 2nd Stage Boot Loader image from the non-volatile memory (NAND/SD/eMMC/QSPI) to Memory (DDR/TCM/OCM) and takes A53/R5 out of reset. It supports multiple partitions, and each partition can be a ...Dec 16, 2023 ... In this video i start by describing the fundamentals on the I2C Buss looking on the start and stop conditions, the 7bit address, ...Linux Drivers. This page is intended to give more details on the Xilinx drivers for Linux, such as testing, how to use the drivers, known issues, etc. The drivers included in the kernel tree are intended to run on the ARM (Zynq, Ultrascale+ MPSoC, Versal) and MicroBlaze Linux.

Part 1 of how to work with both the processing system (PS), and the FPGA (PL) within a Xilinx ZYNQ series SoC. Error: the "NANDgate" verilog file i wrote was...Linux kernel source tree. Contribute to torvalds/linux development by creating an account on GitHub.Part 2 of how to work with the processing system (PS) and FPGA (PL) in a Xilinx ZYNQ series SoC. Questions? DM me on instagram @fpga_guy

Zynq-7000 Embedded Design Tutorial. This document provides an introduction to using the Xilinx® Vitis™ unified software platform with the Zynq®-7000 SoC device. The examples are targeted for the Xilinx ZC702 rev 1.0 evaluation board and the tools used are the Vivado® Design Suite, the Vitis software platform, and PetaLinux.

Insert the Micro SD card loaded with the PYNQ-Z2 image into the Micro SD card slot underneath the board. Connect the USB cable to your PC/Laptop, and to the PROG - UART MicroUSB port on the board. Connect the Ethernet port by following the instructions below. Turn on the PYNQ-Z2 and check the boot sequence by following the instructions below.

Nov 18, 2021 · What is FSBL? First St age Bootloader (FSBL) for Zynq UltraScale+ MPSoC configures th e FPGA with hardware bitstream (if it exists) and loads the Operating System (OS) Image or Standalone (SA) Image or 2nd Stage Boot Loader image from the non-volatile memory (NAND/SD/eMMC/QSPI) to Memory (DDR/TCM/OCM) and takes …Jun 29, 2022 · I2C Tutorial Introduction. I2C is a serial protocol for a two-wire interface to connect low-speed devices like microcontrollers, EEPROMs, A/D and D/A converters, I/O interfaces, and other similar peripherals in embedded systems.It was invented by Philips and now it is used by almost all major IC manufacturers.Hello, I am trying to implement an I2C-Slave (AXI IIC) in a Zynq device. Based on the "xiic_slave_example.c" I could receive some bytes with the iic-module. So far, so good. Because I have to add the slave device to an existing design I have the following data structure: Write to Slave: The master sends the slave address with bit 0 = 0 ...We would like to show you a description here but the site won't allow us.Zynq™ UltraScale+™ MPSoC devices provide 64-bit processor scalability while combining real-time control with soft and hard engines for graphics, video, waveform, and packet processing. Built on a common real-time processor and programmable logic equipped platform, three distinct variants include dual application processor (CG) devices, quad ...

Such modifications include the addition of a second PL fabric clock and the enabling of the I2C interface for the communication of control signals between the Zynq PS and the codec. We will begin by adding an instance of the audio controller IP to the block design. (a) In the Vivado IP Integrator block design canvas, right-click and select Add IP.Zedboard Programming Guide in SDK (Obsolete) This tutorial is obsolete. Check Creating a Baremetal Boot Image for Zynq-7000 Devices for a more recent version. Overview There are three ways you can program the Zedboard: * JTAG * Quad SPI Flash * SD Card This tutorial will walk you through what you need to know to get started on your projects and program your Zedboard using each of the three ...I am looking for a simple tutorial on how to use a PMOD with SPI on a Zedboard using Vivado 2014.3. I have purchased several PMODs recently (Digilent ethernet, SD card, LCP display and Maxim temperature 31723 and RS232 port) but none of them seem to have a tutorial I can make any sense of that uses Vivado. The closest that I have found so far is the "Zynq Workshop for Beginners" by ...Introduction. Zynq UltraScale+ devices integrate a flagship ARM® Cort ex®-A53 64-bit quad-core or dual-core processor, Cortex-R5 dual-core real-time processor in PS, and PL in a single device. The PL includes the programmable logic, configuration logic, and associated embedded functions. The PS comprises the ARM Cortex-A53 MPCore CPUs unit, Cortex-R5 processors, on-chip memory, external ...Subscribe to the latest news from AMD. Facebook; Instagram; Linkedin; Twitch; Twitter; Youtube; Subscriptions; CompanyZynq PS I2C Cadence Driver/Device Reset. I am using the Cadence I2C drivers with the ZYNQ PS I2C busses. It seems my Bus 0 is in a stuck position with both lines high, but I don't want to reset my board in case I don't get it in this state again. Is there a way to reset an I2C device driver or bus from linux user space?Feb 20, 2023 Knowledge. Title. 70871 - Understanding AXI IIC protocol - behavioral simulation use case. Description. It is easy to understand the AXI IIC simulation by using pseudo steps like the following, and comparing them against the behavior you are seeing. Keep a copy of the following steps and you can then edit it if you are omitting or ...Under the Recent Projects column, click the edt_zc702 design that you created in Example 1: Creating a New Embedded Project with Zynq SoC. In Flow Navigator window, click Open Block Design under IP Integrator. Add the AXI GPIO and AXI Timer IP: In the Diagram window, right-click in the blank space and select Add IP.This kit features a Zynq™ UltraScale+™ MPSoC EV device with video codec and supports many common peripherals and interfaces for embedded vision use case. The included ZU7EV device is equipped with a quad-core ARM® Cortex™-A53 applications processor, dual-core Cortex-R5 real-time processor, Mali™-400 MP2 graphics processing unit, 4KP60 ...The Ethernet transceiver (U24) clock is supplied by the ZYNQ (U31). However, it also works on a board on which a crystal is mounted. SD card boot support is required. Short the resistor (R2577) Mount the tactile switch (S3), the capacitor (C2410) and the resistor (R2641A). The resistor (R2641A) can be shorted instead of mounting a 0 ohm ...Are you in the market for a new Mazda vehicle, but aren’t sure where to find the nearest dealership? Don’t worry – we’ve got you covered. In this step-by-step tutorial, we will gui...petalinux-package --boot --fsbl zynq_fsbl.elf --fpga system_wrapper.bit --uboot. Copy BOOT.BIN and image.ub (roughly 11 MB) to the SD card. The SD card has to be formatted as FAT32. Boot the ZedBoard with the SD card (make sure the jumpers are set correctly). PetaLinux netboot using TFTP. Use SD card for initial boot.Contains an example on how to use the XIic driver directly. This example consists of a Interrupt mode design which shows the usage of the Xilinx iic device and XIic driver to exercise the EEPROM. The XIic driver uses the complete FIFO functionality to transmit/receive data. This example writes/reads from the lower 256 bytes of the IIC EEPROMS.The Mars XU3 system-on-chip (SoC) module combines Xilinx's Zynq UltraScale+ MPSoC device with fast DDR4 SDRAM, eMMC flash, quad SPI flash and a Gigabit Ethernet PHY, USB 3.0 and thus forms a complete and powerful embedded processing system.Add this topic to your repo. To associate your repository with the zynq-7010 topic, visit your repo's landing page and select "manage topics." GitHub is where people build software. More than 100 million people use GitHub to discover, fork, and contribute to over 420 million projects.This simply creates an I2C bus. TwoWire I2CBME = TwoWire(0); In the setup (), initialize the I2C communication with the pins you've defined earlier. The third parameter is the clock frequency. I2CBME.begin(I2C_SDA, I2C_SCL, 400000); Finally, initialize a BME280 object with your sensor address and your TwoWire object.We would like to show you a description here but the site won't allow us.

Are you looking for a hassle-free way to create beautiful gift certificates? Look no further. In this step-by-step tutorial, we will guide you through the process of customizing a ...3.1) Click the Add IP button and search for ZYNQ. Double click on ZYNQ7 Processing System to place the bare Zynq block. 3.2) Click the Run Block Automation link. Your Zynq block should now look like the picture below. 3.3) Click the Add IP icon again, this time search for “gpio” and add the AXI GPIO core.The Configuration Security Unit (CSU) is the Zynq UltraScale+ functional block that provides interfaces required to implement the secure system. There is also a section in the Zynq UltraScale+ MPSoC Embedded Design Tutorial - about security and secure boot. For more information, refer to the Zynq Ultrascale+ MPSoC Security Features page.Mar 11, 2024 · 1、背景介绍ZYNQ在PS部分有两路I2C,但有时候存在不够用的情况,这时就需要使用PL部分的I2C IP核(以下简称AXI I2C)。关于该IP核的信息可以参考XILINX官方的datasheet,不过在使用AXI I2C时需要进行修改才能够正确进行收发数。 2、硬件配置如下图 …This kit features a Zynq™ UltraScale+™ MPSoC EV device with video codec and supports many common peripherals and interfaces for embedded vision use case. The included ZU7EV device is equipped with a quad-core ARM® Cortex™-A53 applications processor, dual-core Cortex-R5 real-time processor, Mali™-400 MP2 graphics processing unit, …Subscribe to the latest news from AMD. Facebook; Instagram; Linkedin; Twitch; Twitter; Youtube; Subscriptions; CompanyTable 1-1: Zynq UltraScale+ MPSoC ZU7EV Features and Resources Feature Resource Count Quad core Arm Cortex-A53 MPCore 1 Dual core Arm Cortex-R5 MPCore 1 Mali-400 MP2 GPU 1 H.264/H.265 VCU 1 HD banks Two banks, total of 48 pins HP banks Six banks, total of 312 pins MIO banks Three banks, total of 78 pins PS-GTR transceivers (6 Gb/s) Four PS-GTR ...Dec 30, 2020 · 前言. 在ZYNQ上中有USB的控制器,最近在使用pluto sdr进行数据传输的时候,觉得串口太慢,但是也没有找到关于USB的在裸机下的资料。. 一般都是用操作系统来做的,这就很郁闷了啊,我一个 FPGA 小白,现在还不会linux啊。. 然后就上GitHub上找了找看看有没有人做过 ...

Mar 30, 2020 · Welcome to the Zynq beginners workshop. The purpose of this document is to give you a hands-on introduction to the Zynq-7000 SoC devices, and also to the Xilinx Vivado Design Suite. Throughout the course of this guide you will learn about the Zynq SoC solution step-by-step, and gain the knowledge and experience you need to create your …3.1) First, make sure that JP1 does not have a jumper and that the Arty is plugged into your computer via micro-USB cord. Once the board is plugged in you should see something like this. 3.2) Click Program device (in the green bar) then xc7a35t_0, select your .bit file in the bitstream file box, and click Program.This is a tutorial targeted at Verilog and Python users who wish to use Zynq 7000 to do Verilog FPGA module development and interface their Verilog in the PL to the PS system. I went through this learning curve a few months ago and wanted to share my experience to "pay it forward". I used a TUL-2 Board. Design Steps and decisions The general flow of design steps I followed are: Develop the ...Dec 1, 2023 · Since the Arty Z7 uses a Zynq-7000 FPGA which has a physical ARM-core processor built into the programmable logic of the FPGA, the Zynq Processing System IP is what provides the hooks to that ARM processor to the rest of the design to access it. Click the + button to bring up the IP Catalog and type "Zynq" into the search bar. Double-click on ...Zynq™ UltraScale+™ MPSoC 器件不仅提供 64 位处理器可扩展性,同时还将实时控制与软硬件引擎相结合,支持图形、视频、波形与数据包处理。. 置于包含通用实时处理器和可编程逻辑的平台上,三个不同变体包括双核应用处理器 (CG) 器件、四核应用处理器和 GPU (EG ...This tutorial will show how to build an example hardware design that can be used to show how the PYNQ GPIO class can be used to control Zynq PS GPIOWhat is FSBL? First St age Bootloader (FSBL) for Zynq UltraScale+ MPSoC configures th e FPGA with hardware bitstream (if it exists) and loads the Operating System (OS) Image or Standalone (SA) Image or 2nd Stage Boot Loader image from the non-volatile memory (NAND/SD/eMMC/QSPI) to Memory (DDR/TCM/OCM) and takes A53/R5 out of reset. It supports multiple partitions, and each partition can be a ...Documentation. Training & Support. The AMD MicroBlaze™ processor offers a range of customizable, easy-to-integrate, 32-bit/64-bit microprocessor configurations based on the efficient RISC Harvard architecture. The MicroBlaze processor offers flexibility, allowing for a wide range of customizations with peripheral, memory, and interface features.This is a tutorial targeted at Verilog and Python users who wish to use Zynq 7000 to do Verilog FPGA module development and interface their Verilog in the PL to the PS system. I went through this learning curve a few months ago and wanted to share my experience to "pay it forward". I used a TUL-2 Board. Design Steps and decisions The general flow of design steps I followed are: Develop the ...Zynq I2C 통신의 기본 Zynq I2C 통신은 Zynq 플랫폼에서 데이터 전송을 위한 핵심 메커니즘입니다. Zynq 기반 시스템에서 I2C를 구현하는 방법은 매우 유연하며 효율적입니다. 기본 설정, 구성, 그리고 I2C 디바이스와의 상호 작용 방법을 이해하는 것이 중요합니다.Summary. Communication protocols, including I2C, SPI, and UART, are essential for enabling seamless data exchange and communication between digital systems and external devices. Implementing these protocols in Verilog requires understanding their specifications, designing the interface, and handling data transfer and control signals accurately.Are you in the market for a new Mazda vehicle, but aren’t sure where to find the nearest dealership? Don’t worry – we’ve got you covered. In this step-by-step tutorial, we will gui...How can I transfer data from PL to PS using standart I/O like I2C, SPI or UART on Zynq. I am finding many tutorial but I did not found the example about hardware design in Vivado. I am using Microzed Board right now. Please give me some ideas about HW design. Processor System Design And AXI. Liked.The Configuration Security Unit (CSU) is the Zynq UltraScale+ functional block that provides interfaces required to implement the secure system. There is also a section in the Zynq UltraScale+ MPSoC Embedded Design Tutorial - about security and secure boot. For more information, refer to the Zynq Ultrascale+ MPSoC Security Features page. · Quick-Start tutorial for the Digilent ZYBO Zynq-7010 FPGA board using ISE 14/PlanAhead. tutorial embedded fpga zybo zynq-7010 planahead Updated Mar 16, 2014; ... It is example of work with Si570 across I2C. standalone linux-arm zynq-7010 si570 Updated May 15, 2018; C; GOOD-Stuff / spi-fpga-uploader Star 2. Code Issues ...PicoZed™ is a highly flexible, rugged, System-On-Module, or SOM that is based on the Xilinx Zynq®-7000 All Programmable (AP) SoC. Toggle navigation . Products. Products. Amplifiers & Comparators; Analog Switches & Multiplexers ... Tutorial 08 PS I2C PMOD. Vivado 2016.4 Version. Vivado 2016.2 Version. Tutorial 09 PL I2C PMOD. Vivado 2016.4 ...PYNQ-Z1 Reference Manual The PYNQ-Z1 board is designed to be used with PYNQ, a new open-source framework that enables embedded programmers to exploit the capabilities of Xilinx Zynq All Programmable SoCs (APSoCs) without having to design programmable logic circuits. Instead the APSoC is programmed using Python, with the code developed and tested directly on the PYNQ-Z1.Zynq UltraScale+ MPSoC Embedded Design Tutorial. This document provides an introduction to using the Vivado® Design Suite flow for the Xilinx® …

Managing the Zynq UltraScale+ Processing System in Vivado¶ Now that you have added the processing system for the Zynq MPSoC to the design, you can begin managing the available options. Double-click the Zynq UltraScale+ Processing System block in the Block Diagram window. The Re-customize IP view opens, as shown in the following figure.

Step 1: Create the Hardware Platform: Note: you can skip this step by using the pre-built HDF file delivered with this blog post. Background: This section covers the steps to follow when you want to create custom hardware for your board using Vivado 2018.3. From Vivado we will output a Hardware Description File (HDF).

Under the Tools & IP tab, Click on "RF Evaluation Tool and Board Setup" to download the software, then unzip the install package in your desired location. Double-click "Setup_RF_DC_Evaluation_UI.exe". NOTE: An administrator account on your laptop/PC might be necessary to complete the install. Click next and select the options you desire ...Note: An Example Design is an answer record that provides technical tips to test a specific functionality on Zynq-7000. A tip can be a snippet of code, a snapshot, a diagram or a full design implemented with a specific version of the Xilinx tools. It is up to the user to "update" these tips to future Xilinx tools releases and to "modify" the Example Design to fulfill their needs.by: AMD. Equipped with the industry's only single-chip adaptable radio device, the Zynq™ UltraScale+™ RFSoC ZCU216 evaluation kit, is the ideal platform for both rapid prototyping and high-performance RF application development. Price: $15,546.00. Part Number: EK-U1-ZCU216-V1-G. Lead Time: 8 weeks.In I2C Bus, NXP semiconductor changed to TI. Figure 1-15 is updated. R249 was added to Figure 1-17. In Table 1-22, reference designator DS12 changed to DS14. U3 level shifter was changed to TXS0104E in Figure 1-19 and Table 1-21. The User I/O section was updated. Figure 1-21 added two LEDs. Table 1-23 added Net Name PS_LED1 and ... Zynq-7000 …Nov 18, 2021 · What is FSBL? First St age Bootloader (FSBL) for Zynq UltraScale+ MPSoC configures th e FPGA with hardware bitstream (if it exists) and loads the Operating System (OS) Image or Standalone (SA) Image or 2nd Stage Boot Loader image from the non-volatile memory (NAND/SD/eMMC/QSPI) to Memory (DDR/TCM/OCM) and takes …We would like to show you a description here but the site won't allow us.Zynq ® UltraScale+™ MPSoCs. The Zynq UltraScale+ MPSoC family has different products, based upon the following system features: • Application processing unit (APU): Dual or Quad-core Arm ® Cortex ®-A53 MPCore CPU frequency up to 1.5 GHz • Real-time processing unit (RPU): Dual-core Arm Cortex ®-R5F MPCore CPU frequency up to 600 MHz

anma skschicas masturbandomeseller82_5421508cdcc345075ecbf9bdd905afebactress tina Zynq i2c tutorial sks znan ba znan [email protected] & Mobile Support 1-888-750-5805 Domestic Sales 1-800-221-6182 International Sales 1-800-241-4899 Packages 1-800-800-6550 Representatives 1-800-323-7738 Assistance 1-404-209-4416. This tutorial is on "Interfacing Rpi SenseHAT with AMD-Xilinx Kria KR260 and Petalinux". Tools Used on this Tutorial are: Vivado 2022.2; ... Following are the IPs Cores used in the Vivado design for creating this "Sense HAT- I2C interface" working on Kria KR260. Zynq® Ultrascale+™ MPSoC.. what is a stock How can I transfer data from PL to PS using standart I/O like I2C, SPI or UART on Zynq. I am finding many tutorial but I did not found the example about hardware design in Vivado. I am using Microzed Board right now. Please give me some ideas about HW design. Processor System Design And AXI. Liked.Aug 9, 2023 · Ensure that the Output format is set to BIN. In the Basic page, browse to and select the Output BIF file path and output path. Next, add boot partitions using the following steps: Click Add to open the Add Partition view. In the Add Partition view, click the Browse button to select the FSBL executable. mack eppinger and sons funeralcraftsman 21 inch snow blower won Compiling the device tree. The device tree comes in three forms: A text file (*.dts) — "source". A binary blob (*.dtb) — "object code". A file system in a running Linux' /proc/device-tree directory — "debug and reverse engineering information". In a normal flow, the DTS file is edited and compiled into a DTB file using a ... sks madrbzrgsks mwdl ash New Customers Can Take an Extra 30% off. There are a wide variety of options. The course spans a comprehensive curriculum that encompasses three fundamental digital communication protocols: Serial Peripheral Interface (SPI), Universal Asynchronous Receiver-Transmitter (UART), and Inter-Integrated Circuit (I2C). Each of these protocols plays a critical role in modern electronics and embedded systems, and mastering them is ...Apr 29, 2020 ... | Xilinx FPGA Programming Tutorials. Simple Tutorials for Embedded Systems•52K views · 17:00. Go to channel · 3 PYTHON AUTOMATION PROJECTS FOR ....frequency jitter changed from 20 ppm to 50 ppm. In I2C Bus, NXP semiconductor changed to TI. Figure 1-15 is updated. R249 was added to Figure 1-17. In Table 1-22, reference designator DS12 changed to DS14. U3 level shifter was changed to TXS0104E in Figure 1-19 and Table 1-21. The User I/O section was updated. Figure 1-21 added two LEDs.